The invention relates to a processor unit for a data-processing-aided electronic control system in a motor vehicle. Here, the term xe2x80x9ccontrol systemxe2x80x9d is used in its broader sense to also include automatic control functions.
The rising number of electronically implemented motor vehicle control functions and their increasing mutual coupling has led to a clear growth in the complexity, along with corresponding difficulties with respect to the development and mastery, of the entire electronic system of the vehicle. The growing complexity of such control systems is caused, for example, by the increase of system functions of a superset character (for example, on-board network management, system diagnosis, vehicle data storage, and the like). Other causes are an increase in the demand for additional interfaces for superset vehicle functionalities (for example, for chip cards) in connection with newer requirements which are based on the increasing telematics functionality, the desire for personal customizing and band limited programming of the vehicle. This trend simultaneously results in a rapid rise of the demand for computing speed in instances where the processor units are used in the control system, as well as in the required storage capacity.
The increasing desire to provide additional functionalities with respect to mobility, communication, information, safety and entertainment in motor vehicles, such as passenger cars also exists. An additional factor is the increasing tendency toward series vehicles which are developed in parallel and a shortening of the development times of these series, as well as the demand for flexibility in reacting to external market requirements. It is therefore desirable to provide a flexible, standardized and open foundation for the electronic infrastructure of motor vehicles which is capable of taking into account such developments at acceptable costs.
Traditionally, data-processing-aided electronic control systems in motor vehicles were developed such that a separate control unit was assigned to each function to be implemented electronically, for example, one unit for the engine control, one for the antilock system, one for a door locking system and/or an electronic driving block, etc. These individual control units were networked to form a multiple control unit arrangement, for example, via a CAN data bus. In such a conventional multiple control unit arrangement, few or only minor interactions occur between the functions implemented by the individual control units. This conventional system design therefore places physical control units in the foreground, as opposed to placing logic functions in the foreground.
In the case of this typical conventional control unit network structure, superset functions and the application logic exist in almost every control unit. In addition, this conventional networked structure of control units of equal rank or processor units representing control units, often requires that many of such control units have multiple bus connections to different networks which exist in the vehicle. With respect to easily converting messages from one system interface to another, this results in a considerable limitation of the flexibility of the system. This also causes high bus loads, as well as execution time delays.
In German Published Patent Applications DE 196 16 346 A1 and DE 196 16 753 A1, data-processing-aided electronic control systems are disclosed which have a multiple control unit arrangement of several control units which are connected via a data bus network and which can be used in motor vehicles. These systems contain a central control unit in the form of a processor unit with a so-called power PC microcontroller. Because of their RISC architecture, such members of the so-called power PC processor family are particularly suitable for high speed processing of control tasks. In the system disclosed in German Patent Document DE 196 16 346 A1, special measures are utilized to ensure that only a small number of electric connections and only one data bus system are required for a video controller. In the system disclosed in German Patent Document DE 196 16 753 A1, a hierarchical processor architecture with at least two processor levels, which are each optimized for certain control tasks, is specifically provided in a processor unit and used to control the data bus.
It is an object of the present invention to provide a processor unit of the initially mentioned type which can be used as a superset control unit for a data-processing-aided control system operating in real time in a motor vehicle. This processor unit has a design which is as flexible, standardized and open as possible. This is so that changes and/or updates, particularly with respect to the respective appropriate computing speed and varying configuration of the electronic system of the vehicle according to the grade of expansion, series, etc., can be implemented at comparatively low costs.
This and other objects and advantages are achieved by the processor unit according to the invention, in which, within its functional structure, the processor unit contains a scalable computing unit and a vehicle interface unit as separate structural components. The scaling capacity of the computing unit ensures an easy adaptation to different computing speed requirements which, in particular, increase with time. The separation of the scalable computing unit, on the one hand, and the vehicle interface unit, on the other hand, in the layout of the logic design of the processor unit promotes this scaling capacity. This also facilitates the adaptation of the electronic system of the vehicle to different configurations via dislocation of the interface functionalities, which conventionally are not separated from the computing unit in the functional structure. Moreover, this further facilitates the combination of different configurations within the vehicle interface unit, which is functionally separated from the computing unit. Here, the vehicle interface unit is an interface unit which communicates with the computing unit and contains interface functionalities which in a conventional manner, are to be provided in motor vehicles. The processor unit designed in such a manner can be provided in an open and scalable family of different variants with a graded capability. This processor is particularly suitable for use as a superset control unit within a data-processing-aided electronic control system operating in real time within a motor vehicle.
In such a system, normally only limited computing speed resources and a static software configuration are available. Here, the electronic data processing functionality is embedded into the superset system of the electronic system of the vehicle while supporting this system as a so-called embedded system. This embedded system does not appear directly to the user. By using the processor unit according to the invention in a system of this type, data-intensive and computing-intensive parts of the control function, as well as the coordination of decentralized automatic control functions and superset functions are assumable by this processor unit. As a result, other control units can be relieved of such functions and can therefore have a simpler design. The processor unit, which can be used in this manner for performing superset tasks within the vehicle electronic network, can be based for this purpose particularly on a scalable computer architecture. This computer architecture can be in the form of a power PC architecture and can be used in arbitrary vehicle series without the connection of any periphery.
In a further developed embodiment according to the invention, a processor unit contains, as a third separate structural component within its functional structure, a communication coprocessor for implementing data communication operations between the scalable computing unit and the pertaining periphery, for example, physical layers of the design structure of the system. By using this communication coprocessor, the CPU of the computing unit can be relieved from interface-related operations, which is very advantageous particularly when there is a plurality of such system interfaces. The communication coprocessor is implemented in the structure of the logic design as an independent structural component, which is separate from the scalable computing unit and the vehicle interface unit. As a result, the loading of the CPU due to interrupts and computing operations is clearly reduced. Only frames required by the CPU have to be transmitted to it, and only complex operations on frames must be implemented by the CPU. Here, the term xe2x80x9cframexe2x80x9d defines the message frame on the respective data transmission system.
In a further developed embodiment according to the invention, the communication coprocessor contains within its functional structure, a bandwidth adapter as a structural component via which incoming messages can be transmitted at a transmission frequency which differs from the receiving frequency. Thus, for example, messages can be transmitted to the CPU at a transmission frequency which is lower than the reception frequency in order to significantly relieve the CPU from transmitted interrupts. As required, messages can also be transmitted to a component which is connected to the bandwidth adapter at a transmission frequency which is higher than the reception frequency. As a result, this component can be provided with messages at its customary message frequency without any additional adaptation measures. Here, a hardware implementation of the bandwidth adapter in the communication coprocessor is advantageous, since this is particularly suitable for an application in the real-time control system of a motor vehicle and permits a further relief of the CPU of the scalable computing unit.
In an embodiment of a processor unit further developed according to the invention, the communication coprocessor contains within its functional structure a Gateway processor implemented in hardware as a structural component. The hardware implementation of the Gateway processor causes a further relief of the CPU of the computing unit with respect to such Gateway functions and is particularly suitable for use in the real-time control system of a motor vehicle.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.